The present invention relates to a multiple channel interface between a two systems. More specifically, the present invention relates to a method and structure for providing a multiple channel interface between a computer system and a communication device.
FIG. 1 is a block diagram of a conventional computer system 100 which includes a central processing unit (CPU) 1, an arbiter circuit 2, a main memory circuit 3, a PCI bus 4, a first in, first out (FIFO) memory device 5 and a communication controller 6. FIFO memory device 5 includes a PCI interface circuit 5a and a communication interface circuit 5b. 
PCI bus 4 operates at a frequency of 33 MHz. Communication controller 6 typically operates at a frequency which is lower than 33 MHz. For example, communication controller 6 can transmit voice data at a frequency of approximately 1.2 kHz or high-speed LAN information at a frequency of approximately 20 MHz. Communication controller 6 typically has multiple data channels which are coupled to PCI bus 4 through FIFO memory device 5.
For data transfer between communication controller 6 and PCI bus 4, communication controller 6 interrupts PCI bus 4 for relatively long periods of time, thereby significantly slowing down the operating speed of PCI bus 4. CPU 1 cannot access PCI bus 4 until after communication controller 6 has completed the data transfer.
Moreover, FIFO memory device 5 has a fixed number of channels and a fixed number of entries per channel. Thus, different FIFO memory devices are necessary for use with different communication devices.
It would therefore be desirable to have a multi-channel data transfer circuit which overcomes the shortcomings of prior art FIFO memory devices.
Accordingly, the present invention provides a multi-channel data transfer circuit and method which provides an interface between a computer system and a multi-channel communication controller. The data transfer circuit is programmable to provide a selectable number of communication channels between the computer system and the communication controller. The data transfer circuit is further programmable to provide a selectable number of entries in each of the communication channels. In a particular embodiment, FIFO memories within the data transfer circuit are logically partitioned to provide the desired number of communication channels and the desired number of entries per channel. Each of the communication channels can have the same number of entries. Alternatively, different communication channels can have different numbers of entries. As a result, the data transfer circuit can be configured in view of the particular requirements of the computer system and the communication controller.
The data transfer circuit includes a multi-channel transmit circuit for providing data values from the computer system to the communication controller, and a multi-channel receive circuit for providing data values from the computer communication controller to the computer system. Both the transmit and receive circuits include caching systems to promote burst read and write accesses to the computer system. These burst accesses advantageously minimize the amount of time that the communication controller ties up the bus of the computer system.
The present invention will be more fully understood in light of the following detailed description taken together with the drawings.